AXI Protocol based Interview Questions

Hi everyone,

To support those preparing for hardware verification and design roles or for engineers working with the protocol daily, I’ve compiled a curated list of AXI Protocol Interview Questions.

To help you navigate the content effectively, I have categorized the questions into three levels:

Basic Level:

1. What are the key features of the AXI protocol?
2. Why does AXI have 5 channels? Name them and explain why they are separate?
3. Why does the Read operation only have 2 channels while Write has 3?
4. Explain the VALID/READY handshake. What are the three possible scenarios for these signals?
5. Define "Beat", "Transfer", and "Burst"?
6. What are the three burst types in AXI? (FIXED, INCR, WRAP). Give a real-world use case for each ?
7. What are the four AXI response types? Explain the scenario when respective response type is received ?
8. Can AXI read and write happen simultaneously?
9. Can address and data phases overlap?
10. Why there is no read response channel in AXI ? 
11. How do you check handshake correctness?
12. In AXI4, can a slave send a Write Response (BVALID) before the master has finished sending all the data beats (WVALID/WLAST)?

Mid Level:

1. Explain the AXI Write & Read transaction sequence with channel flow ?
2. What are the different burst types supported in AXI (FIXED, INCR, WRAP)? Explain in detail ?
3. Explain out-of-order transaction support in AXI. How is it achieved?
4. What is data interleaving in AXI? Is it supported in AXI4?
5. What is the role of AXI ID (transaction ID) in AXI channels?
6. How are read/write transactions associated in AXI (especially for out-of-order)?
7. What happens if a slave does not support out-of-order responses?
8. How do you verify out-of-order responses?
9. How does back-pressure work in AXI?
10. What is the difference between transaction ordering and response ordering?
11. Can multiple outstanding transactions exist?
12. How do you detect deadlock in AXI?
13. What happens if WLAST is asserted early?
14. Can RLAST come without valid data?
15. Can write response come before all data is sent?
16. Can read data start before address handshake?
17. In AXI4, if AxLEN = 7 and burst type is INCR, what is the actual number of data beats transferred?

Advance Level:

1. Calculate the address sequence for a WRAP burst with: Start_Address = 0x38, AxLEN = 3, and AxSIZE = 2 (4 bytes)?
2. Why must the Start_Address be aligned for a WRAP burst? (follow up question)
3. Calculate the effective bandwidth of a 128-bit AXI bus running at 400MHz, assuming 80% efficiency due to address overhead and arbitration ?
4. If a 64-bit master writes to address 0x03, explain how the WSTRB (Write Strobes) bits are set for the first beat?
5. Why is a burst not allowed to cross a 4KB boundary?
6. Explain the difference between Read Interleaving and Out-of-Order (OoO) completion?
7. If Master A sends two requests (ID: 0 and ID: 1), can the Slave return ID 1 first?  If Master A sends two requests (both ID: 0), can the Slave return the second one first?
8. A master wants to transfer 128 bytes starting at 0x100 using INCR bursts. Assume AxSIZE = 4 bytes (32-bit data bus). What is the minimum number of bursts needed if the slave supports max burst length of 16 beats?
9. Calculate the wrap boundary and address sequence for a WRAP burst: AxSIZE=4 bytes, AxLEN=7 (8 beats), start address=0x1C?
10. If a master issues two read transactions with the same ID but different addresses, and the slave returns data out-of-order, how does the master associate responses?