Hi everyone,
To support those preparing for hardware verification and design roles or for engineers working with the protocol daily, I’ve compiled a curated list of AXI Protocol Interview Questions.
To help you navigate the content effectively, I have categorized the questions into three levels:
Basic Level:
- What are the key features of the AXI protocol?
- Why does AXI have 5 channels? Name them and explain why they are separate?
- Why does the Read operation only have 2 channels while Write has 3?
- Explain the VALID/READY handshake. What are the three possible scenarios for these signals?
- Define "Beat", "Transfer", and "Burst"?
- What are the three burst types in AXI? (FIXED, INCR, WRAP). Give a real-world use case for each ?
- What are the four AXI response types? Explain the scenario when respective response type is received ?
- Can AXI read and write happen simultaneously?
- Can address and data phases overlap?
- Why there is no read response channel in AXI ?
- How do you check handshake correctness?
- In AXI4, can a slave send a Write Response (
BVALID) before the master has finished sending all the data beats (WVALID/WLAST)?
